Japanese Patent Application Laid-Open Publication No. 2013-12648 (Patent Document 1) describes a semiconductor device in which a semiconductor chip is mounted over a solder resist film of a wiring substrate with an underfill resin interposed therebetween, and a manufacturing method thereof. Patent Document 1 describes a technique in which a projecting electrode is arranged on a narrow portion of a bonding lead which is exposed from the solder resist film and the electrode is connected to the lead via the solder material.
In addition, Japanese Patent Application Laid-Open Publication No. 2000-77471 (Patent Document 2) describes a technique in which a projecting electrode (bump) is arranged in a part with a large width of a bonding lead (conductive pattern) exposed from a solder resist film and the electrode is connected to the lead via a solder material.
In addition, Japanese Patent Application Laid-Open Publication No. 2007-266136 (Patent Document 3) describes a technique in which each solder resist layer formed on a top surface and a bottom surface of a wiring substrate includes glass cloth to thereby reinforce mechanical strength of the wiring substrate.